Package-on-package assembly and method for manufacturing the same

A package-on-package (PoP) assembly, comprising:

• a bottom die package comprising
• an interposer having a first side and a second side opposite to the first side;
• at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps;
• at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the dummy chip is directly mounted on a passivation layer of the interposer;
• a dielectric layer covering the at least one active chip and the at least one dummy chip;
• at least one TSV connecter penetrating through the dielectric layer and the dummy chip;
• a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip;
• and
• a plurality of solder bumps mounted on the second side;
• a top die package mounted on the bottom die package.