Chip package and method for manufacturing the same

A chip package comprising:

• a first metallic chip carrier and a second metallic chip carrier;
• at least one chip carried by the first metallic chip carrier;
• a first redistribution layer disposed over the at least one chip over a side of the at least one chip facing away from the first metallic chip carrier;
• a second redistribution layer disposed over the at least one chip over the side of the at least one chip facing away from the metallic chip carrier and disposed over the first redistribution layer,
• wherein a surface of the package facing away from the chip comprises one or more unexposed portions of the second redistribution layer for electrical coupling with external components;
• encapsulation material encapsulating the at least one chip, the first metallic chip carrier, the second metallic chip carrier, the first redistribution layer and partially encapsulating the second redistribution layer;
• and
• at least one contact hole extending through the encapsulation material to electrically couple the at least one chip with the first redistribution layer and/or the second redistribution layer.

A modular chip package comprising:

• a metallic chip carrier;
• at least one chip carried by the metallic chip carrier;
• encapsulation material encapsulating the at least one chip and the metallic chip earner;
• a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip;
• and
• an electrically conductive layer disposed over the metallic chip carrier opposite the plurality of redistribution layers;
• and
• at least one electrical component disposed over the electrically conductive layer opposite the plurality of redistribution layers.

A chip package comprising:

• a metallic chip carrier;
• at least one chip carried by the metallic chip carrier;
• encapsulation material encapsulating the at least one chip and the metallic chip earner;
• a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip;
• and
• an electrically conductive layer disposed over the metallic chip carrier opposite the plurality of redistribution layers;
• and
• at least one electrical component disposed over the electrically conductive layer opposite the plurality of redistribution layers.