Chip package structure and manufacturing method thereof

A chip package structure comprising:

• a lead frame comprising:
• a first patterned metal layer comprising a chip pad and a plurality of bonding pads, the chip pad comprising a first main body, a plurality of first extensions and a plurality of first recesses, the first extensions extending in a direction away from the first main body, such that the first extensions and the first main body collectively define the first recesses, each of the first extensions respectively extending between every two adjacent bonding pads, and at least one edge of each of the first extensions aligned to at least one edge of the adjacent bonding pads, the first recesses being located at a periphery of the chip pad, the bonding pads being respectively located in the first recesses, and a first groove existing between each of the bonding pads and the chip pad;
• a second patterned metal layer connected to the first patterned metal layer, the second patterned metal layer comprising a heat dissipation block and a plurality of terminal pads, the heat dissipation block being thermally coupled to the chip pad and comprising a plurality of second recesses, the second recesses being located at a periphery of the heat dissipation block, the terminal pads being respectively located in the second recesses and electrically connected to the corresponding bonding pads, a second groove existing between each of the terminal pads and the heat dissipation block;
• and
• an insulation layer located between the bonding pads and the terminal pads;
• a chip disposed on the first main body of the chip pad and electrically connected to the bonding pads;
• and
• an encapsulant covering the first patterned metal layer and the chip.