US 9,437,514 B2 · Semiconductor package with coated side walls and method of manufacture

Abstract

A semiconductor package including an integrated device, the package having a front side, a back side and side walls linking the front and back sides, wherein each side wall is coated, to at least 80% of its area, with a coating material different from the material(s) of the back and front sides. A method of manufacturing a semiconductor package by providing an assembly containing an array of the packages, the assembly having thickness d0 and being attached to a dicing tape of thickness dd, fabricating a set of first dicing streets with width w1 and depth d1<(d0+dd), filling the first dicing streets at least partially with a coating material, and fabricating, in the coating material in each first dicing street, a second dicing street with width w2≦w1 and depth d2≧d0 but <(d0+dd).

Claims19

Dependent claims

A semiconductor package, comprising

an integrated device comprising a sensitive element,
a front side of a material A wherein material A represents a packaging for the integrated device,
a back side of a material B opposite to the front side,
side walls that link the front side and the back side,
each side wall being coated with a coating material to at least 80% of its area,
the coating material being different from the material A and being different from the material B,
wherein one of:
the front side is free from the coating material;
or
the coating material coated on at least one of the side walls wraps around a lateral end of the front side and covers less than 20% of the area of the front side.

7 more elements

A method for manufacturing a semiconductor package, comprising:

(a) providing a semiconductor package assembly containing an array of semiconductor packages for manufacturing a plurality of semiconductor packages, each semiconductor package comprising
an integrated device comprising a sensitive element,
a front side representing a packaging for the integrated device,
a front side of the semiconductor package assembly comprising access openings to the sensitive elements,
the semiconductor package assembly having a thickness d0 and being attached to a dicing tape of thickness dd with the front side of the semiconductor package assembly facing the dicing tape,
(b) fabricating a set of first dicing streets around semiconductor packages or groups of semiconductor packages with a width w1 and a depth d1<(d0+dd) from a backside of the semiconductor package assembly,
(c) filling the set of first dicing streets at least partially with a coating material,
(d) fabricating, in the coating material in each first dicing street of the set, a second dicing street with a width w2<=w1 and a depth d2>=d0 and d2<(d0+dd), resulting in semiconductor packages with side walls, each side wall being coated with the coating material to at least 80% of its area.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor package with coated side walls and method of manufacture

Life of this patent

Semiconductor package with coated side walls and method of manufacture

Life of this patent

Abstract

Claims19