Array substrate and fabrication method thereof, and display device

A fabrication method of an array substrate, comprising:

• forming a thin film transistor;
• forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor;
• forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode;
• treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode;
• and
• forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer,
• wherein the method further comprises:
• forming a pixel electrode layer;
• coating a photoresist on the pixel electrode layer, exposing and developing the photoresist by using a dual-tone mask to form a photoresist fully-reserved region, a photoresist partially-reserved region and a photoresist fully-removed region, the photoresist fully-reserved region corresponding to a region where the pixel electrode is to be formed, the photoresist partially-reserved region corresponding to a region where the via-hole conductive layer is to be formed, and the photoresist fully-removed region corresponding to other region;
• removing the pixel electrode layer in the photoresist fully-removed region by etching;
• removing the photoresist in the photoresist partially-reserved region by ashing to form the via-hole conductive layer;
• treating the via-hole conductive layer with remaining photoresist as a mask, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode;
• and
• removing the remaining photoresist to obtain the pixel electrode.

A fabrication method of an array substrate, comprising:

• forming a thin film transistor;
• forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor;
• forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode;
• treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode;
• and
• forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer,
• wherein the method further comprises:
• forming a pixel electrode layer;
• performing a patterning process on the pixel electrode layer by using a first single-tone mask to form the pixel electrode and the via-hole conductive layer;
• and
• treating the via-hole conductive layer by using a second single-tone mask, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode.