US 9,437,485 B2Granted

Method for line stress reduction through dummy shoulder structures

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsCheng-Cheng Kuo, Tzu-Chun Lo, Ming-Hsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao

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Abstract

Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

Claims20

Dependent claims

A method comprising:

forming a plurality of dense conductive lines, an isolated line, and a plurality of conductive shoulder lines on a substrate, the plurality of dense conductive lines extending in a first direction, the isolated line being in the vicinity of the plurality of dense conductive lines and extending in the first direction,
wherein the plurality of conductive shoulder lines includes a first number of conductive shoulder lines on a first side of the isolated line, the first number of conductive shoulder lines connected to the isolated line on the first side and extending therefrom in a second direction that is substantially perpendicular to the first direction, and
wherein the plurality of conductive shoulder lines includes a second number of conductive shoulder lines on a second side of the isolated line that oppose the first side of the isolated line, the second number of conductive lines connected to the isolated line on the second side such that there are less conductive shoulder lines connected to the second side of the isolated line than the first side of the isolated line.

Dependencies are inferred from the claim text.

Facts

Application: 14/245,085Filed 4 Apr 2014 · division
Priority: 2 Apr 2010
Published: US 2014/0208283 A124 Jul 2014
Granted: 6 Sep 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/031
Manufacture or treatment: of conductive parts of the interconnections
G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/394
Circuit design at the physical level: routing
H10W 20/40
Interconnections in chips, wafers or substrates: interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or…

Family

Application12/753,272Parent of this division · filed 2 Apr 2010
US 2014/0208283 A1Pre-grant publication · published 24 Jul 2014
US 8,692,351 B2Parent of this division
US 2011/0241207 A1Published application
US 9,437,485 B2This patent

From the US filing history. Foreign family members aren’t listed.

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