US 9,437,472 B2 · Semiconductor line feature and manufacturing method thereof

Abstract

Some embodiments of the present disclosure provide a semiconductor structure with a reduced line feature. The semiconductor structure includes a substrate, a first active region in the substrate and having a first sidewall, a second active region in the substrate and having a second sidewall, an isolation region contacting the first sidewall and the second sidewall. The above-mentioned semiconductor structure possesses a width of a top surface of the isolation region less than 50 nm and a width of a bottom surface of the isolation region more than 20 nm. Some embodiments provide a method for controlling a semiconductor line feature in a wafer, including patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer, forming a trench on the wafer correlated to the line feature by performing a plasma dry etch over the wafer, and filling the trench with isolation materials.

Claims18

Dependent claims

A manufacturing method for a semiconductor isolation structure, comprising:

patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a substrate by performing a first plasma etch at a first temperature;
forming a trench having a sidewall angle greater than 88 degrees in the substrate correlated to the line feature by performing a second plasma etch at a second temperature;
rounding a bottom of the trench by performing a third plasma etch at the second temperature;
and
filling the trench with isolation materials,
wherein the first plasma etch is performed with at least two different plasma densities along a radial direction of the hard mask simultaneously, and the second plasma etch is performed with a uniform plasma density along the radial direction of the hard mask, and
wherein the at least two different plasma densities are formed by applying a current ratio in a range of from about 0.5 to about 0.8 between the current entering a first set of magnetic coils close to a center of the wafer and the current entering a second set of the magnetic coils close to an edge of the wafer.

4 more elements

A method for controlling a semiconductor line feature in a wafer, comprising:

patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer by performing a first plasma etch, comprising:
forming at least two different temperature zones across the wafer, comprising forming concentric-distributed temperature zones with a higher temperature zone close to an edge of the wafer and a lower temperature zone close to a center of the wafer, and the higher temperature zone being three degrees Celsius greater than the lower temperature zone;
and
forming at least two different plasma density zones over the wafer by applying a current ratio lower than 0.8 between the current entering a first set of magnetic coils close to the center of the wafer and the current entering a second set of the magnetic coils close to the edge of the wafer;
forming a trench having a sidewall angel greater than 88 degrees in the wafer correlated to the line feature by performing a second plasma etch over the wafer;
and
filling the trench with isolation materials.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor line feature and manufacturing method thereof

Life of this patent

Semiconductor line feature and manufacturing method thereof

Life of this patent

Abstract

Claims18