LTPS TFT having dual gate structure and method for forming LTPS TFT

A method for forming an LTPS TFT having a dual-gate structure, comprising:

• forming a plurality of patterned a-Si layers disposed on a substrate;
• forming a barrier layer on the plurality of patterned a-Si layers;
• forming a first patterned poly-Si layer and a second patterned poly-Si layer on the barrier layer;
• coating a first photoresist layer on a top surface of the second patterned poly-Si layer and surrounding the second patterned poly-Si layer;
• forming an N-type channel by doping the first patterned poly-Si layer;
• removing the first photoresist layer from the second patterned poly-Si layer;
• forming a gate insulation layer on both of the second patterned poly-Si layer and the first patterned poly-Si layer where the N-type channel is formed;
• forming a second photoresist layer on the gate insulation layer, and doping the second patterned poly-Si layer to form a P+-type layer;
• removing the second photoresist layer from the gate insulation layer, and coating a third photoresist layer on the gate insulation layer;
• removing a part of the third photoresist layer, a part of the gate insulation layer, and a part of the barrier layer by performing exposing and developing processes, for forming a plurality of openings;
• N+doping a part of the patterned a-Si layer and a part of the first patterned poly-Si layer which are not covered by the gate insulation layer;
• forming a plurality of patterned GE layers on the gate insulation layer;
• N−doping the first patterned poly-Si layer and the second patterned poly-Si layer with the plurality of patterned GE layers as a second shielding layer, the plurality of patterned GE layers corresponding to the first patterned poly-Si layer connected to and conducted to the N+-type layer of the patterned a-Si layer, and the plurality of patterned GE layers and the N+-type layer forming a dual-gate structure;
• forming an ILD on the plurality of patterned GE layers and the gate insulation layer;
• forming a plurality of via holes penetrating the ILD and the gate insulation layer;
• and
• forming a plurality of patterned source/drain electrodes through the plurality of via holes, the plurality of patterned source/drain electrodes connected to the P+-type layer which is connected to the second patterned poly-Si layer to for a PMOS, and the plurality of patterned source/drain electrodes connected to the N+-type layer which is connected to the first patterned poly-Si layer to form an NMOS.