Margin tool for double data rate memory systems

A method for testing double data rate transfers of data between a memory controller and a memory device, the method comprising:

• receiving a double data rate strobe placement value indicating where a training sequence performed by the memory controller has placed a double data rate strobe transition within a data eye transferred between the memory device and the memory controller, wherein the double data rate strobe transition is transferred along with the data eye between the memory device and the memory controller;
• receiving a range of double data rate strobe transition settings that transferred data during a testing of double data rate transfers between the memory controller and the memory device;
• comparing the double data rate strobe placement value to the range of double data rate strobe transition settings;
• and
• outputting information representing where the double data rate strobe placement value resides within the range of double data rate strobe transition settings.

A method for designing a double data rate (“DDR”) memory system comprising a DDR memory controller coupled to a DDR memory device, the method comprising:

• performing a training sequence comprising the DDR memory controller conducting transfers of test data between the DDR memory device and the DDR memory controller to establish a timing location of an initial DDR data strobe with respect to its corresponding data line coupled between the DDR memory device and the DDR memory controller;
• performing a testing process that is operated independently from the training sequence wherein the testing process comprises sweeping a DDR data strobe transition across repeated transfers of the test data between the DDR memory device and the DDR memory controller, the testing process resulting in a data set indicating which of the repeated transfers of the test data correctly and incorrectly captured the test data;
• comparing the timing location of the initial DDR data strobe to the data set indicating which of the repeated transfers of the test data correctly and incorrectly captured the test data, the comparison resulting in an output indicating how much margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data;
• and
• adjusting the DDR memory system as a function of the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data, wherein the adjusting of the DDR memory system as a function of the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data further comprises modifying circuitry coupling the DDR memory controller to the DDR memory device to thereby modify the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data, wherein the margin of error is modified so that the timing location of the initial DDR data strobe is substantially centered within a data eye representing a range of DDR data strobe timing locations that would correctly capture the test data transferred on the corresponding data line.

A method for designing a double data rate (“DDR”) memory system comprising a DDR memory controller coupled to a DDR memory device, the method comprising:

• performing a training sequence comprising the DDR memory controller conducting transfers of test data between the DDR memory device and the DDR memory controller to establish a timing location of an initial DDR data strobe with respect to its corresponding data line coupled between the DDR memory device and the DDR memory controller;
• performing a testing process that is operated independently from the training sequence wherein the testing process comprises sweeping a DDR data strobe transition across repeated transfers of the test data between the DDR memory device and the DDR memory controller, the testing process resulting in a data set indicating which of the repeated transfers of the test data correctly and incorrectly captured the test data;
• comparing the timing location of the initial DDR data strobe to the data set indicating which of the repeated transfers of the test data correctly and incorrectly captured the test data, the comparison resulting in an output indicating how much margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data;
• and
• adjusting the DDR memory system as a function of the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data, wherein the adjusting of the DDR memory system as a function of the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data further comprises modifying circuitry coupling the DDR memory controller to the DDR memory device to thereby modify the margin for error there is for the initial DDR data strobe to shift and still correctly capture the test data, wherein the DDR memory system comprises the DDR memory controller coupled to the DDR memory device on a printed circuit board.