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US 9,437,325 B2Granted
TFT array substrate, display panel and display device
AssigneesShanghai Tianma Am-Oled Co., Ltd., Tianma Micro-Electronics Co., Ltd.
InventorDong Qian
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Abstract
A TFT array substrate is disclosed. The TFT array substrate includes a plurality of gate lines, and a gate driving circuit connected to the gate lines. The gate driving circuit includes a plurality of stages of shift registers, where odd-numbered stages of shift registers are cascaded-connected to each other, even-numbered stages of shift registers are cascaded-connected to each other, and the odd-numbered stages of shift registers and the even-numbered stages of shift registers are disposed at opposite ends of the gate lines.
Claims8
A TFT array substrate, comprising:
- a plurality of gate lines;
- and
- a gate driving circuit connected to the gate lines, comprising a plurality of stages of shift registers, wherein odd-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, even-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, and the odd-numbered stages of shift registers and the even-numbered stages of shift registers are disposed at both ends of the gate lines, respectively,
- wherein the gate driving circuit further comprises a first pulse signal line, a second pulse signal line, a third pulse signal line and a fourth pulse signal line, and each of the plurality of stages of shift registers comprises a first clock signal terminal, a second clock signal terminal, and a reset terminal,
- wherein the first clock signal terminal of the i-th stage of shift register is connected to the first pulse signal line to receive a first pulse signal;
- the second clock signal terminal of the i-th stage of shift register is connected to the second pulse signal line to receive a second pulse signal,
- wherein the reset terminal of the i-th stage of shift register is connected to the third pulse signal line to receive a third pulse signal, wherein i is a positive integer, and
- wherein the first clock signal terminal of the (i+1)-th stage of shift register is connected to the third pulse signal line to receive the third pulse signal;
- the second clock signal terminal of the (i+1)-th stage of shift register is connected to the fourth pulse signal line to receive a fourth pulse signal;
- and the reset terminal of the (i+1)-th stage of shift register is connected to the second pulse signal line to receive the second pulse signal.
7 more elements
A display panel, comprising a TFT array substrate, where the TFT array substrate comprises:
- a plurality of gate lines;
- and
- a gate driving circuit connected to the gate lines, comprising a plurality of stages of shift registers, wherein,
- odd-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, even-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, and the odd-numbered stages of shift registers and the even-numbered stages of shift registers are disposed at both ends of the gate lines, respectively,
- wherein gate driving circuit further comprises a first pulse signal line, a second pulse signal line, a third pulse signal line and a fourth pulse signal line, and each of the plurality of stages of shift registers comprises a first clock signal terminal, a second clock signal terminal, and a reset terminal,
- wherein the first clock signal terminal of the i-th stage of shift register is connected to the first pulse signal line to receive a first pulse signal;
- the second clock signal terminal of the i-th stage of shift register is connected to the second pulse signal line to receive a second pulse signal;
- and the reset terminal of the i-th stage of shift register is connected to the third pulse signal line to receive a third pulse signal;
- wherein, i is a positive integer,
- wherein the first clock signal terminal of the (i+1)-th stage of shift register is connected to the third pulse signal line to receive the third pulse signal;
- the second clock signal terminal of the (i+1)-th stage of shift register is connected to the fourth pulse signal line to receive a fourth pulse signal, and
- wherein the reset terminal of the (i+1)-th stage of shift register is connected to the second pulse signal line to receive the second pulse signal.
9 more elements
A display device, comprising a TFT array substrate, where the TFT array substrate comprises:
- a plurality of gate lines;
- and
- a gate driving circuit connected to the gate lines, comprising a plurality of stages of shift registers,
- wherein odd-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, even-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, and the odd-numbered stages of shift registers and the even-numbered stages of shift registers are disposed at both ends of the gate lines, respectively,
- wherein the gate driving circuit further comprises a first pulse signal line, a second pulse signal line, a third pulse signal line and a fourth pulse signal line, and each of the plurality of stages of shift registers comprises a first clock signal terminal, a second clock signal terminal, and a reset terminal,
- wherein the first clock signal terminal of the i-th stage of shift register is connected to the first pulse signal line to receive a first pulse signal;
- the second clock signal terminal of the i-th stage of shift register is connected to the second pulse signal line to receive a second pulse signal;
- and the reset terminal of the i-th stage of shift register is connected to the third pulse signal line to receive a third pulse signal;
- wherein, i is a positive integer,
- wherein the first clock signal terminal of the (i+1)-th stage of shift register is connected to the third pulse signal line to receive the third pulse signal;
- the second clock signal terminal of the (i+1)-th stage of shift register is connected to the fourth pulse signal line to receive a fourth pulse signal, and
- wherein the reset terminal of the (i+1)-th stage of shift register is connected to the second pulse signal line to receive the second pulse signal.
9 more elements
Dependencies are inferred from the claim text.