Shift register circuit for preventing malfunction due to clock skew and memory device including the same
AssigneeSK hynix Inc.
InventorSoo-Bin Lim
Life of this patent
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Abstract
A shift register circuit may include a first latch capable of latching an input signal in synchronization with a first clock, a first flip-flop capable of latching the output signal of the first latch in synchronization with a second dock having the same skew as the first clock, a second latch capable of latching the output signal of the first flip-flop in synchronization with a third clock having a different skew from the second clock, and a second flip-flop capable of latching the output signal of the second latch circuit in synchronization with a fourth clock having the same skew as the third clock.
Claims12
A shift register circuit, comprising:
- a first D latch capable of latching an input signal in synchronization with a first clock;
- a first D flip-flop capable of latching an output signal of the first D latch in synchronization with a second clock having the same skew as the first clock;
- a second D latch capable of latching an output signal of the first D flip-flop in synchronization with a third clock having a different skew from the second clock;
- and
- a second D flip-flop capable of latching an output signal of the second D latch circuit in synchronization with a fourth clock having the same skew as the third clock.
A shift register circuit, comprising:
- a first region and a second region,
- wherein the first region comprises:
- a first D latch capable of latching an input signal in synchronization with a first clock, and
- 1st to Nth first D flip-flops connected in series and capable of sequentially latching an output signal of the first D latch in synchronization with the first clock, wherein N is an integer of 2 or more;
- wherein the second region comprises:
- a second D latch capable of latching an output signal of the Nth first flip-flop in synchronization with a second clock;
- and
- 1st to Mth second D flip-flops connected in series and capable of sequentially latching an output signal of the second D latch in synchronization with the second clock, wherein M is an integer of 2 or more;
- and
- wherein a distance between the Nth first D flip-flop of the first region and the second D latch of the second region is at least 10 times longer than a distance between D latches and D flip-flops in previous and next stages within one of the first and second regions.
A memory device, comprising:
- a nonvolatile memory circuit capable of storing repair data;
- data buses capable of transferring the repair data outputted by the nonvolatile memory circuit;
- a shift register circuit comprising first to Nth stages and sequentially activating output signals of the first to Nth stages whenever a clock is activated;
- first to Nth storage circuits each capable of storing the repair data from the data buses in response to an activation of a corresponding output signal of the output signals of the first to Nth stages;
- and
- a plurality of memory banks capable of being repaired using the repair data stored in the first to Nth storage circuits,
- wherein each of the first to Nth stages comprises:
- a D latch capable of latching an input signal in synchronization with the clock;
- and
- a D flip-flop capable of latching an output signal of the D latch in synchronization with the clock, and
- wherein the clock transferred to each of the first to Nth stages have a skew difference there between.
A shift register circuit, comprising:
- a first D latch capable of latching an input signal in synchronization with a clock;
- a first D flip-flop capable of latching an output signal of the first latch in synchronization with the clock;
- a second D latch capable of latching an output signal of the first flip-flop in synchronization with the clock;
- and
- a second D flip-flop capable of latching an output signal of the second latch circuit in synchronization with the clock,
- wherein the first D latch and the first D flip-flop have a delay difference due to having different paths in which they receive the clock from the second D latch and the second D flip-flop.
Dependencies are inferred from the claim text.