Error detection method

A system, comprising:

• a memory array, the memory array includes a first set of word lines and a second set of word lines;
• and
• one or more managing circuits in communication with the memory array, the one or more managing circuits configured to program a first set of data into a first set of memory cells connected to the first set of word lines, the one or more managing circuits configured to determine a baseline programming loop count based on programming the first set of data into the first set of memory cells, the one or more managing circuits configured to program a second set of data into a second set of memory cells connected to the second set of word lines subsequent to programming the first set of data into the first set of memory cells, the one or more managing circuits configured to determine a programming loop count associated with programming the second set of data into the second set of memory cells, the one or more managing circuits configured to detect a deviation from the baseline programming loop count based on the programming loop count, the one or more managing circuits configured to program the second set of data into a third set of memory cells connected to a third set of word lines in response to detecting the deviation, the one or more managing circuits configured to detect the deviation if the programming loop count is greater than the baseline programming loop count by at least a threshold number of program/verify cycles.