US 9,437,320 B1 · Joint detecting and decoding system for nonvolatile semiconductor memory with reduced inter-cell interference

Abstract

A system including a receiving module to receive data from cells of memory, each cell storing multiple bits, each bit corresponding to a different type of page of the memory, the bits stored in a cell denoting a state of the cell, and the data including bits from a page of the memory or states of cells along a word line of the memory. A processor generates a reliability indication for a first portion of the data corresponding to a first cell based on the first portion of the data and one or more second portions of the data corresponding to one or more of the cells that are adjacent to the first cell. A decoder decodes the first portion of the data based on the first portion of the data and the reliability indication for the first portion of the data.

Claims16

Dependent claims

A system comprising:

a receiving module configured to receive data from cells of memory, wherein each of the cells stores multiple bits, wherein each of the bits corresponds to a different type of page of the memory, wherein the bits stored in one of the cells denote a state of the one of the cells, and wherein the data includes (i) bits from a page of the memory or (ii) states of cells along a word line of the memory;
a processor configured to generate a reliability indication for a first portion of the data corresponding to a first cell based on (i) the first portion of the data and (ii) one or more second portions of the data corresponding to one or more of the cells that are adjacent to the first cell;
and
a decoder configured to decode the first portion of the data based on (i) the first portion of the data and (ii) the reliability indication for the first portion of the data.

1 more element

A method comprising:

receiving data from cells of memory, wherein each of the cells stores multiple bits, wherein each of the bits corresponds to a different type of page of the memory, wherein the bits stored in one of the cells denote a state of the one of the cells, and wherein the data includes (i) bits from a page of the memory or (ii) states of cells along a word line of the memory;
generating a reliability indication for a first portion of the data corresponding to a first cell based on (i) the first portion of the data and (ii) one or more second portions of the data corresponding to one or more of the cells that are adjacent to the first cell;
and
decoding the first portion of the data based on (i) the first portion of the data and (ii) the reliability indication for the first portion of the data.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

14/687,267Filed 15 Apr 2015 · us provisional application

Priority

15 Apr 2014

Granted

6 Sep 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

G11C 16/349
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention: arrangements for evaluating…
G11C 8/10
Arrangements for selecting an address in a digital store: decoders
G11C 11/5621
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge storage in…
G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits

Joint detecting and decoding system for nonvolatile semiconductor memory with reduced inter-cell interference

Life of this patent

Joint detecting and decoding system for nonvolatile semiconductor memory with reduced inter-cell interference

Life of this patent

Abstract

Claims16