Method for programming non-volatile memory with reduced bit line interference and associated device

A non-volatile memory device with reduced bit line interference, the non-volatile memory device comprising:

• a plurality of memory cells;
• and
• a chip controller, the chip controller configured to program a set of cells of the plurality of memory cells by:
• shooting a programming voltage across each programming cell, wherein a programming cell is a cell of the set of cells;
• detecting a threshold voltage for each programming cell;
• identifying a fast subset of the set of cells and a slow subset of the set of cells based on at least the detected threshold voltage for each programming cell;
• and
• shooting one or more shots of the programming voltage until the threshold voltage for each programming cell of the set of cells is greater than a verify voltage, wherein for each of the one or more shots, a fast bit line bias is applied to the bit line associated with each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.

A method for reducing bit line interference when programming a non-volatile memory device comprising multi-level cells, the method comprising:

• providing the non-volatile memory device comprising a set of multi-level cells, each cell of the set of multi-level cells associated with a bit line and each cell of the set of multi-level cells associated with a data state to which that cell is to be programmed;
• identifying any cells of the set of multi-level cells having a threshold voltage greater than a verify voltage corresponding to a data state associated with that cell and creating a set of uninhibited cells by inhibiting a programming of cells identified as having a threshold voltage greater than the verify voltage corresponding to the data state associated with that cell;
• shooting a first shot of programming voltage across each cell of the set of uninhibited cells;
• detecting a threshold voltage for each cell of the set of uninhibited cells;
• identifying a fast subset of the set of uninhibited cells and a slow subset of the set of uninhibited cells based on at least the detected threshold voltage for each cell, wherein the fast subset comprises one or more fast cells and the slow subset comprises one or more slow cells;
• and
• shooting one or more subsequent shots of the programming voltage until the threshold voltage for each cell of the set of uninhibited cells is greater than a verify voltage corresponding to the data state associated with the cell, wherein for each of the one or more subsequent shots, a fast bit line bias is applied to each bit line associated with a fast cell and a slow bit line bias is applied to each bit line associated with a slow cell.