Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device comprising:

• a memory cell array including a plurality of memory strings, the memory strings including a first memory string and a second memory string, the first memory string and the second memory string being electrically connected to a first bit line,
• the first memory string including a first memory cell, a second memory cell, a first selection transistor, and a second selection transistor, the first selection transistor being electrically connected to the first memory cell in series, the second selection transistor being electrically connected to the second memory cell in series,
• the second memory string including a third memory cell, a fourth memory cell, a third selection transistor, and a fourth selection transistor, the third selection transistor being electrically connected to the third memory cell in series, the fourth selection transistor being electrically connected to the fourth memory cell in series, and
• a controller configured to perform an erase operation for the first memory string or the second memory string separately.