NAND array architecture for multiple simutaneous program and read

A method of performing multiple-WL & All-BL Read, Erase-Verify, and Program-Verify operations in a HiNAND memory array with BL-hierarchical structure, the method comprising,

• providing a HiNAND memory circuit, the HiNAND memory circuit comprising,
• a matrix of NAND memory cells divided to J Groups in column-direction having N global bit lines (GBLs), each Group being divided to L Segments in the column-direction, each Segment being further divided to K Blocks in the column-direction, each Block comprising N Strings in the column-direction or m Pages in row-direction, each String comprising m NAND memory cells connected in series sandwiched by a first String-select transistor and a second String-select transistor, each NAND memory cell in a Page being associated with a word line (WL), J, L, K, m, and N being integer numbers, wherein J is at least greater than 10;
• a BL-hierarchical structure comprising N metal3 lines corresponding to N metal2 lines and further to N metal1 lines all being parallel to each other in different topological levels along the column-direction, each metal3 line being used as one the N GBLs across all J Groups of NAND memory cells, each metal2 line being used as one of N sub-BL lines (SBLs) associated with each column of NAND memory cells across all Segments in each Group, each metal1 line being used as one of N sub-sub-BL lines (BBLs) across all K Blocks in each Segment;
• a plurality of metal0 lines laid out along the row-direction, the plurality of metal0 lines including at least one common source line connected respectively via the first String-select transistor to each of the N Strings of NAND memory cells in one or more Blocks of one or more Segments of each Group, a first power/Vss line for all J Groups, a second power/Vss line for all L Segments in a Group, and a third power/Vss line for all K Blocks in a pair of Segments in one Group;
• N first GBL-select transistors commonly controlled by a first gate signal to respectively couple the N GBLs with the first power/Vss line;
• N second GBL-select transistors commonly controlled by a second gate signal to respectively couple the N GBLs with the corresponding N SBLs;
• N first SBL-select transistors commonly controlled by a third gate signal to respectively couple the N SBLs with the second power/Vss line;
• N second SBL-select transistors commonly controlled by a fourth gate signal to respectively couple the N SBLs with the corresponding N BBLs;
• N BBL-select transistors commonly controlled by a fifth gate signal to respectively couple the N BBLs with the third power/Vss line;
• and
• a Page Buffer circuit respectively coupled to the N GBLs with latches to store and provide multiple page data in the form of sequential pipe-line;
• pre-discharging N GBLs, N SBLs and N BBLs to Vss=0V;
• precharging the N BBLs and the N SBLs in one or more selected Groups to a pre-charge voltage ranging from Vdd to 7V;
• discharging part of the N BBLs and the N SBLs to 0V in accordance with a page data stored in a selected page of NAND memory cells;
• sharing the pre-charge voltage in the remaining part of the N BBLs and the N SBLs with the corresponding GBLs to generate a reduced GBL voltage;
• multiplying the reduced GBL voltage to be sensed and amplified by a latch sense amplifier to latch the corresponding page data to the Page Buffer circuit for storing as digital bits.