Programming memory with reduced short-term charge loss

A memory device, comprising:

• a set of memory cells connected to a word line, the set of memory cells comprises memory cells with different target data states;
• and
• a control circuit, the control circuit is configured to:
• program the set of memory cells without using a verify test for at least some of the memory cells,
• after the programming of the set of memory cells without using the verify test for the at least some of the memory cells, apply at least one negative voltage to the word line, and
• after the at least one negative voltage is applied to the word line, perform additional programming of the set of memory cells, the additional programming uses a verify test for each memory cell in the set of memory cells.

A memory device, comprising:

• a set of memory cells, the set of memory cells comprises memory cells with different target data states;
• and
• a control circuit, the control circuit:
• programs memory cells of the set of memory cells which have a lowest target data state of the different target data states using incremental step pulse programming;
• determines when the memory cells of the lowest target data state reach a programming milestone;
• in response to the memory cells of the lowest target data state reaching the programming milestone, applies a programming voltage to the set of memory cells for each remaining target data state of the different target data states without performing a verify test;
• after the programming voltage is applied to the set of memory cells for each remaining target data state of the different target data states, applies at least one negative voltage to the set of memory cells;
• and
• after the at least one negative voltage is applied to the set of memory cells, performs additional incremental step pulse programming of the set of memory cells.