Memory devices and programming memory arrays thereof

A memory device, comprising:

• a memory array;
• and
• control logic;
• wherein the control logic is configured to decrease a voltage of a signal applied to a first select gate of the memory array from a first voltage of the signal applied to the first select gate to a second voltage of the signal applied to the first select gate, wherein the first select gate is coupled between a string of memory cells of the memory array and a source of the memory array, and wherein the first select gate is on at the first voltage of the signal applied to the first select gate and turns off before the voltage of the signal applied to the first select gate reaches the second voltage of the signal applied to the first select gate;
• wherein the control logic is configured to decrease a voltage of a signal applied to a second select gate of the memory array from a first voltage of the signal applied to the second select gate to a second voltage of the signal applied to the second select gate, wherein the second select gate is coupled between the string of memory cells and a data line, and wherein the second select gate is on at the first voltage of the signal applied to the second select gate and turns off before the voltage of the signal applied to the second select gate reaches the second voltage of the signal applied to the second select gate;
• and
• wherein the control logic is configured to increase a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell, not targeted for programming, in the string of memory cells to a program voltage after or substantially concurrently with decreasing the voltage of the signal applied to the first select gate from the first voltage of the signal applied to the first select gate to the second voltage of the signal applied to the first select gate and after or substantially concurrently with decreasing the voltage of the signal applied to the second select gate from the first voltage of the signal applied to the second select gate to the second voltage of the signal applied to the second select gate.

A memory device, comprising:

• a memory array;
• and
• control logic;
• wherein the control logic is configured to increase a voltage of a signal applied to a source of the memory array from a first voltage of the signal applied to the source to a second voltage of the signal applied to the source, wherein the source is coupled to a first select gate of the memory array, wherein the first select gate is on when the voltage of the signal applied to the source is at the first voltage of the signal applied to the source and the first select gate turns off before the voltage of the signal applied to the source reaches the second voltage of the signal applied to the source;
• wherein the control logic is configured to increase a voltage of a signal applied to a data line from a first voltage of the signal applied to the data line to a second voltage of the signal applied to the data line, wherein the data line is coupled to a second select gate of the memory array, wherein the second select gate is on when the voltage of the signal applied to the data line is at the first voltage of the signal applied to the data line and the second select gate turns off before the voltage of the signal applied to the data line reaches the second voltage of the signal applied to the data line;
• and
• wherein the control logic is configured to increase a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell, not targeted for programming, in a string of memory cells of the memory array coupled to the first and second select gates to a program voltage after or substantially concurrently with increasing the voltage of the signal applied to the source from the first voltage of the signal applied to the source to the second voltage of the signal applied to the source and after or substantially concurrently with increasing the voltage of the signal applied to the data line from the first voltage of the signal applied to the data line to the second voltage of the signal applied to the data line.