Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsHideyuki Kamata, Toshifumi Minami, Teppei Higashitsuji, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara
Life of this patent
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Abstract
A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.
Claims20
A semiconductor memory device comprising:
- a first memory cell transistor stacked above a semiconductor substrate;
- a second memory cell transistor stacked above the first memory cell transistor;
- first and second word lines electrically connected to gates of the first and second memory cell transistors, respectively;
- and
- a first transfer transistor electrically connected to the first word line and a second transfer transistor electrically connected to the second word line, wherein sizes of the first and second transfer transistors are different.
A semiconductor memory device comprising:
- a plurality of memory cell transistors that are stacked above a semiconductor substrate, the memory cell transistors having sizes that increase in proportion to a distance thereof to the semiconductor substrate;
- a plurality of word lines, each of which is electrically connected to a gate of one of the memory cell transistors;
- a plurality of word line driver circuits, each of which is configured to generate a voltage for one of the word lines;
- and
- a plurality of transistors, each of which is electrically connected at a first end to one of the word line driver circuits and at a second end to one of the word lines, the transistors having sizes that increase in proportion to a distance of the memory cell transistor electrically connected thereto to the semiconductor substrate.
A semiconductor memory device comprising:
- a plurality of memory cell transistors stacked above a semiconductor substrate, a first group of M memory cell transistors being closer to the semiconductor substrate than a second group of N memory cell transistors, where M and N are both greater than 1,
- a plurality of word lines including a first word line electrically connected to a gate of one of the memory cell transistors in the first group and a second word line electrically connected to a gate of one of the memory cell transistors in the second group;
- and
- a row decoder including a first transfer transistor electrically connected to the first word line and a second transfer transistor electrically connected to the second word line, wherein sizes of the first and second transfer transistors are different.
Dependencies are inferred from the claim text.