Three-dimensional resistive memory device with adjustable voltage biasing

A semiconductor memory device, comprising a memory cell array and a control circuit,

• the memory cell array including:
• a plurality of first conductive layers that are stacked in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate;
• a memory layer provided on a side surface of the plurality of the first conductive layers;
• and
• a second conductive layer that extends in the first direction and includes a first side surface that contacts the side surface of the plurality of the first conductive layers via the memory layer,
• a first width in the second direction of the first side surface of the second conductive layer at a first position in the first direction being smaller than a second width in the second direction of the first side surface of the second conductive layer at a second position in the first direction nearer to the substrate than the first position,
• a first thickness in the first direction of the first conductive layer disposed at the first position being larger than a second thickness in the first direction of the first conductive layer disposed at the second position,
• the control circuit being configured to apply a first voltage to a selected first conductive layer of the first conductive layers and provide a second voltage to the second conductive layer, and
• the control circuit being configured to, when the control circuit applies the first voltage to the selected first conductive layer, change a value of the first voltage based on a relative position in the first direction of the selected first conductive layer.