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US 9,437,291 B2Granted
Distributed cascode current source for RRAM set current limitation
AssigneeRambus Inc.
InventorBruce Lynn Bateman
Life of this patent
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Abstract
In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant current mode during an access operation of a memory cell. An array control circuitry may be coupled to the memory cell array, and configured to control the constant current mode and supply an associated select bias voltage to the word line select transistor.
Claims18
An apparatus, comprising:
- a memory cell array, wherein:
- a memory element of a memory cell of the memory cell array is coupled to a source line of the memory cell array through a word line select transistor;
- and
- a current limiting device is coupled between the source line and a supply voltage, the current limiting device to operate in a constant current mode during an access operation of the memory cell;
- and
- an array control circuitry coupled to the memory cell array, the array control circuitry configured to control the constant current mode and supply an associated select bias voltage to the word line select transistor.
3 more elements
A method, comprising:
- selecting at least one memory cell of a memory array;
- biasing a gate of a cell select transistor of the selected memory cell into saturation via a word line corresponding to the selected memory cell;
- biasing a gate of a pull-down transistor that is coupled between a supply voltage and a source or drain of the cell select transistor into saturation;
- and
- activating a bit line correspond to the selected memory cell to switch a memory element of the selected memory cell from a high resistance state to a low resistance state while the gates are biased into saturation.
2 more elements
An apparatus for operating a memory array, the apparatus comprising:
- means for biasing a gate of a cell select transistor of a selected memory cell into saturation via a word line corresponding to the selected memory cell;
- means for biasing a gate of a pull-down transistor that is coupled between a supply voltage and a source or drain of the cell select transistor into saturation;
- and
- means for activating a bit line correspond to the selected memory cell to switch a memory element of the selected memory cell from a high resistance state to a low resistance state while the gates are biased into saturation.
1 more element
Dependencies are inferred from the claim text.