Resistive memory device and operation
AssigneeSamsung Electronics Co., Ltd.
InventorsYong-Kyu Lee, Dae-Seok Byeon, Hyo-Jin Kwon, Hyun-Kook Park, Chi-Weon Yoon, Yeong-Taek Lee
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Abstract
A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.
Claims19
A method of operating a resistive memory device, the method comprising:
- determining whether to perform a refresh operation on memory cells in a memory cell array;
- determining a respective resistance state of each of the memory cells, when the refresh operation is determined to be performed;
- classifying the memory cells within the memory cell array as first memory cells having a resistance state that is equal to or less than a critical resistance level and second memory cells having a resistance state that is greater than the critical resistance level;
- and
- performing a re-writing operation on the first memory cells among the memory cells.
A method of operating a resistive memory device comprising a plurality of memory cells each having a respective resistance state that is one of a plurality of resistance states including first and second groups of one or more resistance states, the first group of resistance states having a higher resistance level than the second group of resistance states, the method comprising:
- reading the resistance states of the plurality of memory cells;
- and
- re-writing the read resistance states to the plurality of memory cells, wherein
- a frequency of performing the re-writing on those of the memory cells having resistance states of the first group of resistance states is less than a frequency of performing the re-writing on those of the memory cells having resistance states of the second group of resistance states.
A memory system including a resistive memory device, the memory system comprising:
- a memory cell array;
- a write/read circuit;
- and
- control logic circuitry, wherein the control logic circuitry is configured to:
- determine whether to perform a refresh operation on memory cells in the memory cell array;
- determine a respective resistance state of each of the memory cells, when the refresh operation is determined to be performed;
- classify the memory cells within the memory cell array as first memory cells having resistance states that are determined to be equal to or less than a critical resistance level and second memory cells having resistance states that are determined to be greater than the critical resistance level;
- and
- instruct the write/read circuit to perform a re-writing operation on the first memory cells among the memory cells.
Dependencies are inferred from the claim text.