Dual mode clock and data scheme for memory programming
AssigneeMicron Technology, Inc.
InventorKerry Dean Tedrow
Life of this patent
Estimating the term…
Abstract
A Phase-Change Memory (PCM) includes a factory programming interface to receive data changing on both a positive transition and a negative transition of a dual edge clock. A transition detector generated internal clock provides a delayed edge to latch the program data. This dual-edge clock scheme provides a doubling in the data transfer rate.
Claims20
A memory device comprising a factory interface to receive factory program data on a data bus switching with a dual edge clock where a transition detector generated internal clock provides a delayed edge to latch the factory program data for storage in the memory device, wherein the factory interface and the transition detector are located in the memory device.
A memory device, comprising:
- a system memory interface to operate in a system mode selected as a default operating mode to receive data and commands from a data bus;
- and
- a factory programming interface to operate in a factory programming mode to receive factory program data on the data bus and a dual edge clock that is used to generate an internal clock from a transition detector to provide a delayed edge to latch the factory program data, wherein the factory programming interface and the transition detector are located in the memory device.
A memory device comprising:
- a memory array;
- a system memory interface operating in a system mode for executing system applications;
- and
- a factory programming interface operating in a factory programming mode to receive program data on a data bus and to generate an internal clock from a transition detector to provide a delayed edge to latch the program data, wherein the factory programming interface is located in the memory device.
Dependencies are inferred from the claim text.