Memory system, method of programming the memory system, and method of testing the memory system

A method of programming a memory system, comprising:

• repetitively performing N program loops for a selected memory cell, where N is a natural number equal to or greater than two, each of the N program loops including a program operation and a program verify operation,
• wherein at least one of the N program loops comprises
• performing the program operation on the selected memory cell and at least one additionally selected memory cell by applying a first voltage to at least one word line to which the selected memory cell and the at least one additionally selected memory cell are connected;
• and
• performing the program verify operation on the selected memory cell by applying a second voltage to a selected word line to which the selected memory cell is connected, and
• wherein program loops other than the at least one of the N program loops comprise
• performing the program operation on the at least one additionally selected memory cell by applying the first voltage to at least one additionally selected word line to which the at least one additionally selected memory cell is connected, the at least one word line including the selected word line and the at least one additionally selected word line;
• performing the program verify operation on the at least one additionally selected memory cell by applying the second voltage to the at least one additionally selected word line;
• performing a re-program operation on the selected memory cell by applying the first voltage to the selected word line;
• and
• performing a re-program verify operation on the selected memory cell by applying the second voltage to the selected word line.

A method of testing a memory system, comprising:

• applying a first voltage to at least one word line to which a first memory cell and at least one additional memory cell are connected, the at least one word line including a first word line to which the first memory cell is connected;
• applying a second voltage to a plurality of string select lines to which the first memory cell and the at least one additional memory cell are connected, the plurality of string select lines including a first string select line to which the first memory cell is connected and at least one additional string select line to which the at least one additional memory cell is connected;
• applying a third voltage to the first word line;
• and
• applying the third voltage to the first string select line, and applying a fourth voltage to the at least one additional string select line,
• wherein the at least one word line further comprises at least one additional word line to which the at least one additional memory cell is connected, and
• the first word line and the at least one additional word line are alternately disposed.