Write address synchronization in 2 read/1write SRAM arrays

A method for operating a memory array comprising at least a first and a second six transistor static random access memory cell, and a first and a second address decoder,

• the first address decoder being electrically conductive connected to a first access transistor of each of the at least two memory cells via one or more first wordlines, the second address decoder being electrically conductive connected to a second access transistor of each of the at least two memory cells via one or more second wordlines, the first address decoder comprising at least a first latch, the second address decoder comprising at least a second latch,
• the first latch comprising a first and a second data input, the first latch being configured to selectively capture data from the first or the second data input, the respective first data input being electrically conductive connected to a first address data path for providing first address data, the respective second data input being electrically conductive connectable by a first multiplexer to a second address data path for providing second address data,
• the second latch comprising a first data input electrically conductive connected to the second address data path,
• the method comprising:
• for a write access to the memory array operating the first multiplexer and the at least two latches in a first write mode including:
• electrically conductive connecting the second data input of the first latch to the second address data path by the first multiplexer;
• and
• capturing second address data by the first latch from its second data input and by the second latch from its first data input;
• and
• for a read access to the memory array operating the first multiplexer and the at least two latches in a read mode including:
• capturing first address data by the first latch from its first data input;
• and
• capturing second address data by the second latch from its first data input.