High performance sense amplifier

A sense amplifier device for sensing a differential signal produced by a memory cell comprising:

• a first n-type metal-oxide-semiconductor field-effect transistor (NMOS) stack having two NMOS devices sharing a gate connection connected to a complementary data line;
• and
• a second NMOS stack having two NMOS devices sharing a gate connection connected to a true data line,
• wherein one of the NMOS devices in the first NMOS stack has a higher gate-to-source voltage and a higher drain-to-source voltage than a gate-to-source voltage and a drain-to-source voltage of at least one of the NMOS devices in the second NMOS stack when the voltage of the complementary data line is higher than the voltage of the true data line, and
• wherein one of the NMOS devices in the second NMOS stack has a higher gate-to-source voltage and a higher drain-to-source voltage than a gate-to-source voltage and a drain-to-source voltage of at least one of the NMOS devices in the first NMOS stack when the voltage of the true data line is higher than the voltage of the complementary data line.

A sense amplifier device comprising:

• a first n-type metal-oxide-semiconductor field-effect transistor (NMOS) stack having exactly two NMOS devices sharing a gate connection connected to a complementary data line;
• a second NMOS stack having exactly two NMOS devices sharing a gate connection connected to a true data line;
• a first p-type metal-oxide-semiconductor field-effect transistor (PMOS) device connected to the two NMOS devices in the first NMOS stack configured to hold a voltage on a node associated with the first NMOS stack;
• and
• a second PMOS device connected to the two NMOS devices in the second NMOS stack configured to hold a voltage on a node associated with the second NMOS stack,
• wherein one of the NMOS devices in the first NMOS stack has a higher gate-to-source voltage and a higher drain-to-source voltage than a gate-to-source voltage and a drain-to-source voltage of at least one of the NMOS devices in the second NMOS stack when the voltage of the complementary data line is higher than the voltage of the true data line, and
• wherein one of the NMOS devices in the second NMOS stack has a higher gate-to-source voltage and a higher drain-to-source voltage than a gate-to-source voltage and a drain-to-source voltage of at least one of the NMOS devices in the first NMOS stack when the voltage of the true data line is higher than the voltage of the complementary data line.