Negative bitline boost scheme for SRAM write-assist

A method of sequentially negatively boosting a bit line voltage for writing data to a memory cell, comprising the steps of:

• during a write enable period connecting a bit line voltage node to a ground node through a switch;
• responsive to a boost signal opening the switch to disconnect the bit line voltage node from the ground node;
• after the switch is opened, initiating driving the bit line voltage node to a first negative voltage;
• and
• after the write enable period, closing the switch to reconnect the bit line voltage node to the ground node.

A SRAM memory comprising:

• a SRAM array;
• a write driver coupled to a bit line voltage node, the write driver passing a voltage of the bit line voltage node to a bit line in the SRAM array;
• a switch coupled between the bit line voltage node and a ground node;
• a boost signal circuit coupled to a control node of the switch, the boost signal circuit providing a boost signal responsive to a write enable signal;
• a first capacitor having a first end coupled to the bit line voltage node and a second end coupled to the control node of the switch;
• a dummy bit line coupled to a dummy write driver, the dummy write driver responsive to a write enable signal to drive the dummy bit line to transition between high and low;
• and
• a detector coupled to the dummy bit line for detecting a transition of the dummy bit line between high and low,
• wherein the boost signal circuit is responsive to an output of the detector for providing the boost signal.