Low latency synchronization scheme for mesochronous DDR system

A method for data synchronization, comprising:

• receiving data, a data clock signal, and a clean clock signal;
• sampling the data using the data clock signal;
• synchronizing the sampled data with the clean clock signal;
• outputting the synchronized sampled data;
• tracking a phase drift between the data clock signal and the clean clock signal;
• and
• pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

An apparatus for data synchronization, comprising:

• means for receiving data, a data clock signal, and a clean clock signal;
• means for sampling the data using the data clock signal;
• means for synchronizing the sampled data with the clean clock signal;
• means for outputting the synchronized sampled data;
• means for tracking a phase drift between the data clock signal and the clean clock signal;
• and
• means for pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

A memory interface, comprising:

• a plurality of synchronization circuits;
• and
• a memory controller configured to output a clock signal and a calibration signal to each of the plurality of synchronization circuits;
• wherein each of the plurality of synchronization circuits is configured to detect a phase difference between the calibration signal and the clock signal at the synchronization circuit, and to report the detected phase difference to the memory controller;
• and
• wherein the memory controller is configured to determine whether outputs of the synchronization circuits are offset by one clock cycle of the clock signal based on the detected phase differences from the plurality of synchronization circuits, and to instruct each of one or more of the synchronization circuits to pull in or push out the respective output by one clock cycle of the clock signal if a determination is made that the outputs of the synchronization circuits are offset by one clock cycle of the clock signal.