Mechanism for data generation in data processing systems

A method, comprising:

• comparing transmit data to a first delayed version of the transmit data to generate a clock enable signal;
• generating a filtered data rate clock signal based on a data rate clock signal and the clock enable signal, wherein the data rate clock signal is provided as the filtered data rate clock signal when the clock enable signal has a first logic state and a predetermined logic state is provided as the filtered data rate clock signal when the clock enable signal has a second logic state;
• and
• generating final transmit data in response to one of rising or falling edges of the filtered data rate clock signal, wherein the final transmit data corresponds to a second delayed version of the transmit data.

An integrated circuit, comprising:

• a first delay unit having an input to receive transmit data and an output to provide a first delayed version of the transmit data;
• a comparator having a first input coupled to receive the transmit data, a second input coupled to receive the first delayed version of the transmit data, and an output coupled to provide a clock enable signal;
• clock control circuitry coupled to receive the clock enable and a data rate clock and coupled to provide a filtered data rate clock, wherein the clock control circuitry is configured to provide the data rate clock as the filtered data rate clock while the clock enable has a first logic state;
• a delay chain having an input to receive the filtered data rate clock and an output coupled to provide a delayed filtered data rate clock;
• and
• a flip flop having a clock input coupled to receive the delayed filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a second delayed version of the transmit data received by the first delay unit.