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US 9,437,274 B1Granted
Memory device
AssigneeSK hynix Inc.
InventorsKwi-Dong Kim, Jun-Hyun Chun
Life of this patent
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Abstract
A memory device may include a plurality of word lines each word line being operably coupled to one or more memory cells; a peripheral circuit suitable for performing first and second refresh operations to the plurality of word lines; wherein the first refresh operation is suitable for preserving stored data for a majority of the memory cells of the memory device and the second refresh operation is suitable for preserving stored data of one or more weak memory cells.
Claims25
A memory device, comprising:
- a plurality of word lines each word line being operably coupled to one or more memory cells;
- a peripheral circuit suitable for performing first and second refresh operations to the plurality of word lines;
- wherein the first refresh operation is suitable for preserving stored data for a majority of the memory cells of the memory device and the second refresh operation is suitable for preserving stored data of one or more weak memory cells.
A memory device, comprising:
- a plurality of word lines coupled to one or more memory cells;
- a peripheral circuit suitable for performing first and second refresh operations to the plurality of word lines;
- a nonvolatile memory unit suitable for storing weak row addresses of one or more weak word lines among the plurality of word lines;
- and
- a refresh control unit suitable for controlling the peripheral circuit to perform the first refresh operation to the plurality of word lines once during a refresh section divided into N numbers (N is a natural number more than two) of sub-refresh sections, and to perform the second refresh operation to the weak word lines during the refresh section,
- wherein the refresh control unit controls the peripheral circuit to perform the first and second refresh operations to each of the weak word lines at an interval of one or more of the N numbers of sub-refresh sections.
3 more elements
A memory device, comprising:
- first to N-th word lines coupled to one or more memory cells;
- a peripheral circuit suitable for performing first and second refresh operations to the plurality of word lines;
- a nonvolatile memory unit comprising first to N-th nonvolatile memory cells suitable for storing first to N-th weak data, which correspond to the respective first to N-th word lines and each of which stores one of first and second values;
- and
- a refresh control unit suitable for controlling the peripheral circuit to sequentially perform the first refresh operation to the plurality of word lines during a refresh section, and to perform the second refresh operation to weak word lines during the refresh section based on the first to N-th weak data.
2 more elements
Dependencies are inferred from the claim text.