Nonvolatile memory apparatus for controlling a voltage level of enabling a local switch
AssigneeSK hynix Inc.
InventorsJae Yun Yi, Seok Pyo Song
Life of this patent
Estimating the term…
Abstract
A nonvolatile memory apparatus includes: a memory cell coupled to a bit line and a source line; a word line configured to select the memory cell; and a local switch block configured to apply a write voltage, a read voltage, and a source line voltage to the bit line and the source line in response to a local switch select signal. In a write or read operation of the nonvolatile memory apparatus, the word line has a first voltage level, and the local switch select signal has a second voltage level higher than the first voltage level.
Claims18
A nonvolatile memory apparatus comprising:
- a memory cell coupled to a bit line and a source line;
- a word line configured to select the memory cell;
- a first local switch block configured to provide at least one of a write voltage, a read voltage, and a source line voltage to the bit line in response to a first local switch select signal;
- a second local switch block configured to provide at least one of the write voltage and the source line voltage to the source line in response to a second local switch select signal;
- a first data write/read circuit configured to provide the write voltage, the read voltage, and the source line voltage to the first local switch block in response to a column address signal, a write signal, data, and a read signal;
- and
- a second data write/read circuit configured to provide the write voltage and the source line voltage to the second local switch block in response to the column address signal, the write signal, the data, and the read signal,
- wherein the first and second local switch select signals are enabled at logic high levels and the first and second local switch select signals are enabled at different voltage levels from each other.
A nonvolatile memory apparatus comprising:
- a variable resistor having a first end coupled to a bit line;
- a cell transistor having a first end coupled to a second end of the variable resistor, a second end of the cell transistor coupled to a source line, and a gate of the cell transistor coupled to a word line;
- a first local switch configured to apply at least one of a write voltage, a read voltage, and a source line voltage to the bit line in response to a first local switch select signal;
- and
- a second local switch configured to apply at least one of the write voltage and the source line voltage to the source line in response to a second local switch select signal,
- wherein the first and second local switch select signals are enabled at logic high levels and the first and second local switch select signals are enabled at different voltage levels from each other.
A nonvolatile memory apparatus comprising:
- a memory cell coupled to a bit line and a source line;
- a word line configured to select the memory cell;
- a first local switch block configured to selectively provide a write voltage, a read voltage, and a source line voltage to the bit line in response to a first local switch select signal according to operations of the nonvolatile memory apparatus;
- and
- a second local switch block configured to selectively provide the write voltage and the source line voltage to the source line in response to a second local switch select signal according to operations of the nonvolatile memory apparatus,
- wherein the first and second local switch select signals are enabled at a logic high level and the first and second local switch select signals are enabled at different voltage levels with each other.
Dependencies are inferred from the claim text.