Unipolar programmable metallization cell

An integrated circuit, comprising:

• a plurality of bit lines and a plurality of word lines;
• an array of memory cells and a corresponding array of access devices, coupled to the plurality of bit lines and the plurality of word lines, the memory cells in the array respectively including a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between corresponding word lines and bit lines;
• and
• sense circuitry coupled to the array of memory cells, to sense whether a selected memory cell has a threshold below a read threshold;
• control circuitry coupled to the plurality of bit lines and the plurality of word lines to apply bias arrangements for operation of the memory cells, including:
• a read bias arrangement to sense a resistance state of a selected memory cell;
• a first write bias arrangement to induce the formation of a bridge in the dielectric layer of a first selected memory cell establishing a first resistance state in the first selected memory cell, the first write bias having a polarity between a word line and a bit line connect to the first selected memory cell and inducing a current having a direction through the first selected memory cell;
• and
• a second write bias arrangement to induce disintegration of a bridge in the dielectric layer of a second selected memory cell establishing a second resistance state in the second selected memory cell, the second write bias having a polarity between a word line and a bit line connect to the second selected memory cell and inducing a current having said direction through the second selected memory cell.