Memory operation latency control
AssigneeMacronix International Co., Ltd.
InventorsChun-Hsiung Hung, Han-Sung Chen, Ming-Chao Lin
Life of this patent
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Abstract
An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.
Claims17
A method of operating an integrated circuit with memory, comprising:
- performing a first operation on a memory array;
- and
- in response to a read command sequence after said first operation, performing a first read operation characterized by a first latency or performing a second read operation characterized by a second read latency, the first read operation being performed if a time delay between the first operation and the read command sequence is not less than a timing parameter, the second read operation being performed if said time delay is less than the timing parameter.
An integrated circuit, comprising:
- a memory array;
- and
- control circuitry coupled to the memory array, wherein the control circuitry:
- in response to a read command sequence, performing a first read operation characterized by a first latency or performing a second read operation characterized by a second read latency, the first read operation being performed if the time delay between a previous operation and the read command sequence is less than a timing parameter, the second read operation being performed if said time delay is not less than the timing parameter.
A method of operating an integrated circuit with memory, comprising:
- performing a first read operation on a memory array in response to a first read command sequence initiated at a first time, the first read operation characterized by a first read latency;
- and
- in response to a second read command sequence initiated at a second time, the second time occurring after the first read operation terminates, performing a second read operation characterized by a second read latency less than the first read latency, if a time difference between an end of the first read operation and the second time is less than a timing parameter, else performing said first read operation.
Dependencies are inferred from the claim text.