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US 9,437,262 B2Granted
Memory controller and associated signal generating method
AssigneeMStar Semiconductor, Inc.
InventorsZong-Han Wu, Chen-Nan Lin, Chung-Ching Chen, Yung Chang
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Abstract
A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.
Claims20
A signal generating method of a memory controller, for controlling a memory module, comprising:
- generating a first clock signal having a signal period of a unit time;
- generating a command signal having a signal period of the unit time, wherein the command signal comprises a plurality of command groups each having a first command and a second command that are consecutive;
- generating an address signal set having a signal period of twice of the unit time;
- setting a first signal edge of the first clock signal to within a latching interval of the command signal;
- setting a second signal edge of the first clock signal to within the latching interval of the command signal and a latching interval of the address signal set;
- and
- controlling the memory module according to the command signal and the address signal.
4 more elements
A memory controller, connectable to a memory module, comprising:
- a clock generating unit, configured to generate a first clock signal having a signal period of a unit time to the memory module;
- a control signal translating unit, configured to generate a command signal having a signal period of the unit time to the memory module, wherein the command signal comprises a plurality of command groups each having a first command and a second command that are consecutive;
- and
- an address translating unit, configured to generate an address signal set having a signal period of twice of the unit time to the memory module;
- wherein, the clock generating unit sets a first signal edge of the first clock signal to within a latching interval of the command signal, and sets a second signal edge of the first clock signal to within the latching interval of the command signal and a latching interval of the address signal set.
2 more elements
Dependencies are inferred from the claim text.