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US 9,437,261 B2Granted
Memory controller and information processing device
AssigneeFujitsu Limited
InventorNoriyuki Tokuhiro
Life of this patent
Estimating the term…
Abstract
A memory controller has a first variable delay circuit that delays a data strobe signal received from a memory, and a second variable delay circuit that variably delays a data signal which is received from the memory and is synchronous with the data strobe signal, and that is set a second delay amount which is different from a first delay amount of the first variable delay circuit.
Claims8
A memory controller comprising:
- a first variable delay circuit that delays a data strobe signal received from a memory;
- a second variable delay circuit that delays a data signal which is received from the memory and is synchronous with the data strobe signal;
- a first data signal latch circuit that latches a delay data signal, which is delayed by the second variable delay circuit, in response to an internal clock;
- a phase comparator that generates a first variable delay setting value corresponding to a first delay amount of the first variable delay circuit such that a phase difference between the data strobe signal and the internal clock is reduced, and sets the first variable delay setting value to the first variable delay circuit;
- and
- an adder that adds to the first variable delay setting value an offset value such that a setup margin and a hold margin of the first data signal latch circuit are corrected, to generate a second variable delay setting value corresponding to a second delay amount of the second variable delay circuit, and sets the second variable delay setting value to the second variable delay circuit.
3 more elements
An information processing device comprising:
- an arithmetic processing unit;
- and
- a memory controller that executes memory access to a memory in response to a memory access request issued by the arithmetic processing unit, wherein the memory controller includes:
- a first variable delay circuit that delays a data strobe signal received from a memory;
- a second variable delay circuit that delays a data signal which is received from the memory and is synchronous with the data strobe signal;
- a first data signal latch circuit that latches a delay data signal, which is delayed by the second variable delay circuit, in response to an internal clock;
- a phase comparator that generates a first variable delay setting value corresponding to a first delay amount of the first variable delay circuit such that a phase difference between the data strobe signal and the internal clock is reduced, and supplies the first variable delay setting value to the first variable delay circuit;
- and
- an adder that adds to the first variable delay setting value an offset value such that a setup margin and a hold margin of the first data signal latch circuit are corrected, to generate a second variable delay setting value corresponding to a second delay amount of the second variable delay circuit, and supplies the second variable delay setting value to the second variable delay circuit.
6 more elements
A control method for controlling a memory controller that includes a first variable delay circuit that delays a data strobe signal received from a memory;
- a second variable delay circuit that delays a data signal which is received from the memory and is synchronous with the data strobe signal;
- a first data signal latch circuit that latches a delay data signal, which is delayed by the second variable delay circuit, in response to an internal clock;
- and a phase comparator that generates a first variable delay setting value corresponding to a first delay amount of the first variable delay circuit such that a phase difference between the data strobe signal and the internal clock is reduced and set the first variable delay setting value to the first variable delay circuit,
- the method comprising:
- adding to the first variable delay setting value an offset value such that a setup margin and a hold margin of the first data signal latch circuit are corrected, to generate a second variable delay setting value corresponding to a second delay amount of the second variable delay circuit;
- and
- setting the second variable delay setting value to the second variable delay circuit.
4 more elements
Dependencies are inferred from the claim text.