Memory system including memory chips having serially and parallel arranging input/output

A memory system comprising:

• a first memory chip including first to Nth cell arrays, each including a plurality of memory cells;
• a second memory chip, stacked on the first memory chip, including first to Nth cell arrays, each including a plurality of memory cells, and to be stacked on the first memory chip;
• and
• one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays of the first memory chip and to the first to Nth cell arrays of the second memory chip, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays of the first memory chip and to the first to Nth cell arrays of the second memory chip;
• the first to Nth data output units are configured to serially arrange data received from corresponding cell arrays of the first to Nth cell arrays of the first memory chip and from corresponding cell arrays of the first to Nth cell arrays of the second memory chip, and output the serially-arranged data to the corresponding first to Nth data input/output pads;
• and
• the first to Nth data input units are configured to parallel-arrange data inputted through the corresponding first to Nth data input/output pads, and input the parallel-arranged data to the corresponding cell arrays of the first to Nth cell arrays of the first memory chip and to the corresponding cell arrays of the first to Nth cell arrays of the second memory chip.