Sensing circuit, memory device and data detecting method

A memory device, comprising:

• a data bit line;
• a reference bit line;
• a memory cell coupled to the data bit line;
• a reference cell coupled to the reference bit line;
• a sensing resistor having a first end coupled to a power supply voltage node and a second end;
• a reference resistor having a first end coupled to the power supply voltage node and a second end;
• a comparator having
• a first input coupled to the second end of the sensing resistor, the first input configured to be coupled to the memory cell via the data bit line,
• a second input coupled to the second end of the reference resistor, the second input configured to be coupled to the reference cell via the reference bit line, and
• an output, the comparator configured to generate at the output an output signal indicating a logic state of data stored in the memory cell based on a comparison between voltages at the first input and the second input;
• and
• a reference column selector switch arranged between the reference bit line and the second input of the comparator, wherein the reference column selector switch is configured to selectively couple the reference bit line to the second input of the comparator;
• a resistance calibration circuit configured to automatically calibrate a total resistance of the sensing resistor or the reference resistor, the resistance calibration circuit comprising:
• a first resistor, a first PMOS transistor, and a first NMOS transistor coupled in parallel with each other;
• and
• a second resistor, a second PMOS transistor, and a second NMOS transistor coupled in parallel with each other;
• wherein
• the sensing resistor or the reference resistor to be calibrated by the resistance calibration circuit comprises a third resistor, a third PMOS transistor, and a third NMOS transistor coupled in parallel with each other;
• gates of the first through third PMOS transistors are coupled with each other;
• and
• gates of the first through third NMOS transistors are coupled with each other.

A method of detecting data stored in a memory cell, the method comprising:

• connecting a data bit line associated with the memory cell to a sensing resistor via a first node;
• connecting a reference bit line associated with a reference cell to a reference resistor via a second node in response to a decoded column address signal;
• causing a cell current to flow from a power supply voltage node, through the sensing resistor, through the first node, via the data bit line and through the memory cell;
• causing a reference current to flow from the power supply voltage node, through the reference resistor, through the second node, via the reference bit line and through the reference cell;
• comparing voltages at the first and second nodes to detect a logic state of the data stored in the memory cell;
• and
• automatically calibrating a resistance of at least one of the sensing resistor or the reference resistor, said calibrating comprising:
• generating a first control signal based on a first comparison of a first reference voltage with a first voltage caused by a first current flowing through a first resistor, a first PMOS transistor and a first NMOS transistor,
• supplying the first control signal to gates of first through third PMOS transistors,
• generating a second control signal based on a second comparison of a second reference voltage with a second voltage caused by a second current flowing through a second resistor, a second PMOS transistor and a second NMOS transistor, and
• supplying the second control signal to gates of first through third NMOS transistors;
• wherein
• the first resistor, the first PMOS transistor, and the first NMOS transistor are coupled in parallel with each other;
• the second resistor, the second PMOS transistor, and the second NMOS transistor are coupled in parallel with each other;
• and
• the sensing resistor or the reference resistor being calibrated comprises a third resistor, the third PMOS transistor, and the third NMOS transistor coupled in parallel with each other.