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US 9,437,256 B2Granted
Data shifting
AssigneeMicron Technology, Inc.
InventorsTimothy B. Cowles, Steven M. Bodily
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.
Claims19
An apparatus, comprising:
- a first memory cell and a second memory cell;
- a first sense line coupled to the first memory cell;
- a second sense line coupled to the second memory cell;
- a first transistor device including a first node coupled to the first sense line;
- a second transistor including a first node coupled to the second sense line;
- a third transistor coupled between the first sense line and the second sense line;
- a first sensing circuitry coupled to a second node of the first transistor;
- a second sensing circuitry coupled to a second node of the second transistor;
- and
- a fourth transistor coupled between the first node of the first transistor and the second node of the second transistor and including a control node coupled to a second control node supplying a second control signal.
7 more elements
A method comprising:
- reading out data from a first memory cell to a first sense line while disconnecting the first sense line from a second sensing circuitry to which the first sense line is coupled;
- connecting the first sense line to a first sensing circuitry so that the first sensing circuitry amplifies the data on the first sense line to produce amplified data;
- disconnecting the first sense line from the first sensing circuitry;
- and
- storing the amplified data into a second memory cell through a second sense line coupled to the second memory cell.
2 more elements
An apparatus, comprising:
- a first word line;
- first and second sense lines each intersecting the first word line;
- first and second memory cells disposed at an intersection of the first word line and the first sense line and an intersection of the first word line and the second sense line;
- first and second sensing circuits;
- a first switch coupled between the first sense line and the first sensing circuit;
- a second switch coupled between the second sense line and the second sensing circuit;
- and
- a third switch coupled between the first sensing circuit and the second sense line.
5 more elements
An apparatus, comprising:
- a first memory cell and a second memory cell;
- a first sense line coupled to the first memory cell;
- a second sense line coupled to the second memory cell;
- a first transistor device including a first node coupled to the first sense line;
- a second transistor including a first node coupled to the second sense line;
- a third transistor coupled between the first sense line and the second sense line;
- a first sensing circuitry coupled to a second node of the first transistor;
- a second sensing circuitry coupled to a second node of the second transistor;
- and
- wherein a control node of the first transistor and a control node of the second transistor are coupled to a third control node supplying a control signal.
7 more elements
An apparatus, comprising:
- a first memory cell and a second memory cell;
- a first sense line coupled to the first memory cell;
- a second sense line coupled to the second memory cell;
- a first transistor device including a first node coupled to the first sense line;
- a second transistor including a first node coupled to the second sense line;
- a third transistor coupled between the first sense line and the second sense line;
- a first sensing circuitry coupled to a second node of the first transistor;
- a second sensing circuitry coupled to a second node of the second transistor;
- and
- wherein the first memory cell and the second memory cell are coupled to a same first word line.
7 more elements
An apparatus, comprising:
- a first memory cell and a second memory cell;
- a first sense line coupled to the first memory cell;
- a second sense line coupled to the second memory cell;
- a first transistor device including a first node coupled to the first sense line;
- a second transistor including a first node coupled to the second sense line;
- a third transistor coupled between the first sense line and the second sense line;
- a first sensing circuitry coupled to a second node of the first transistor;
- a second sensing circuitry coupled to a second node of the second transistor;
- and
- a first accumulator coupled to the first sense line to temporarily store a data value on the first sense line.
7 more elements
Dependencies are inferred from the claim text.