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US 9,437,254 B2Granted
Method of dynamically selecting memory cell capacity
AssigneeMicron Technology, Inc.
InventorFederico Pio
Life of this patent
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Abstract
A method is provided for using a multi-level cell memory device. The method includes writing first data to a first portion of a memory array using a first number of state levels for memory cells of the first portion of the memory array. The method further includes re-writing second data to a second portion of the memory array using a second number of state levels for memory cells of the second portion of the memory array. The second number is different from the first number.
Claims19
A method of using a multi-level cell memory device, the method comprising:
- responsive to a first instruction, writing first data to a first portion of a memory array using a first number of threshold voltage values corresponding to a respective first number of states, wherein the first instruction includes a first operating parameter indicating particular values of the first number of threshold voltage values;
- and
- responsive to a second instruction, writing second data to a second portion of the memory array using a second number of threshold voltage values corresponding to a respective second number of states, wherein the second instruction includes a second operating parameter indicating particular values of the second number of threshold values, and wherein the second number of states is different from the first number of states.
A memory device comprising:
- a plurality of multi-level memory cells;
- and
- circuitry to:
- responsive to a first instruction, write first data to a first portion of a memory array using a first number of threshold voltage values corresponding to a respective first number of states, wherein the first instruction includes a first operating parameter indicating particular values of the first number of threshold voltage values;
- and
- responsive to a second instruction, write second data to a second portion of the memory array using a second number of threshold voltage values corresponding to a respective second number of states, wherein the second instruction includes a second operating parameter indicating particular values of the second number of threshold values, wherein the second number of states is different from the first number of states.
3 more elements
A memory system comprising:
- a memory device comprising a plurality of multi-level memory cells and a memory controller to:
- responsive to a first instruction, write first data to a first portion of a memory array using a first number of threshold voltage values corresponding to a respective first number of states, wherein the first instruction includes a first operating parameter indicating particular values of the first threshold voltage values;
- responsive to a second instruction, write second data to a second portion of the memory array using a second number of threshold voltage values corresponding to a respective second number of states, wherein the second instruction includes a second operating parameter indicating particular values of the second number of threshold values, and wherein the second number of states is different from the first number of states;
- and
- a processor configured to provide access to the plurality of multi-level memory cells.
2 more elements
Dependencies are inferred from the claim text.