Gate driving circuit and display device including the same

A display device comprising:

• a display panel including a plurality of gate lines, a plurality of data lines crossing the gate lines, and a plurality of pixels respectively connected to a selected one of the gate lines and a selected one of the data lines;
• a data driver configured to transmit a plurality of data signals to the data lines, respectively;
• a gate driver including a plurality of stages and configured to transmit a plurality of gate output signals to the gate lines, respectively;
• and
• a timing controller configured to control the gate driver and the data driver,
• wherein each stage includes:
• a first input portion configured to apply an input signal to a first node based at least in part on a first clock signal;
• a first output portion configured to output a second clock signal as a gate output signal based at least in part on a first node signal applied to the first node;
• a second input portion configured to apply the first clock signal to a second node based at least in part on the first node signal;
• a second output portion configured to output a first voltage as the gate output signal based at least in part on a second node signal applied to the second node;
• and
• an output control portion configured to activate the first output portion based at least in part on an output control signal,
• wherein the display panel is flexible;
• wherein the display device further comprises a flexibility detector configured to i) detect a non-display region of the flexible display panel and ii) transmit non-display region information relating to the non-display region to the timing controller,
• wherein the timing controller is further configured to output the output control signal having a first logic level and the first and second clock signals having a second logic level in non-display stages corresponding to the non-display region using the non-display region information, and wherein the first and second logic levels are respectively logical high and logical low levels.

A display device, comprising:

• a display panel including a plurality of gate lines, a plurality of data lines crossing the gate lines, and a plurality of pixels respectively connected to a selected one of the gate lines and a selected one of the data lines;
• a data driver configured to transmit a plurality of data signals to the data lines, respectively;
• a gate driver including a plurality of stages and configured to transmit a plurality of gate output signals to the gate lines, respectively;
• and
• a timing controller configured to control the gate driver and the data driver,
• wherein each stage includes:
• a first input portion configured to apply an input signal to a first node based at least in part on a first clock signal;
• a first output portion configured to output a second clock signal as a gate output signal based at least in part on a first node signal applied to the first node;
• a second input portion configured to apply the first clock signal to a second node based at least in part on the first node signal;
• a second output portion configured to output a first voltage as the gate output signal based at least in part on a second node signal applied to the second node;
• and
• an output control portion configured to activate the first output portion based at least in part on an output control signal,
• wherein the display panel is foldable, and
• wherein the timing controller is configured to output the output control signal having a first logic level and the first and second clock signals having a second logic level in non-display stages corresponding to a non-display region of the foldable display panel when the display panel is folded, and wherein the first and second logic levels are respectively logical high and logical low levels.