Liquid crystal display (LCD) device

A liquid crystal display (LCD) device, comprising:

• a plurality of pixels which are formed at crossing portions at which a plurality of column data lines cross a plurality of row scanning lines, wherein the pixel comprises:
• a display element in which a space, between a pixel electrode and a common electrode opposite to each other, is filled with a liquid crystal and sealed;
• a first switching unit that performs sampling for a display on each frame data of an input video signal using a plurality of sub frames having a display period of time shorter than one frame period of time through the column data line;
• a first holding unit that
• configures an static dynamic random access memory (SRAM) together with the first switching unit, and
• holds sub frame data obtained by the sampling performed by the first switching unit;
• a second switching unit that causes the sub frame data held in the first holding unit to be output;
• and
• a second holding unit that
• configures a dynamic random access memory (DRAM) together with the second switching unit, and
• applies output data, in which memory content is rewritten according to the sub frame data which is held in the first holding unit and is input through the second switching unit, to the pixel electrode,
• a pixel control unit that performs an operation of
• repeating writing the sub frame data in the first holding unit in units of rows in the plurality of pixels,
• turning on the second switching units of all the plurality of pixels by a trigger pulse after the sub frame data is written in all the plurality of pixels, and
• rewriting memory content of the second holding units of the plurality of pixels according to the sub frame data that is held in the first holding unit, in units of sub frames;
• and
• a timing control unit that is composed of an inverter chain circuit that performs control such that a delay of a certain period of time is sequentially given to a timing at which the pixel control unit turns on the second switching unit in units of rows of pixels,
• wherein
• the timing control unit is composed of a plurality of the inverter chain circuits divided in units of rows of pixels in a row direction and each inverter chain circuit starts to be driven at the same time according to a common trigger pulse.

A liquid crystal display (LCD) device, comprising:

• a plurality of pixels which are formed at crossing portions at which a plurality of column data lines cross a plurality of row scanning lines, wherein the pixel comprises:
• a display element in which a space, between a pixel electrode and a common electrode opposite to each other, is filled with a liquid crystal and sealed;
• a first switching unit that performs sampling for a display on each frame data of an input video signal using a plurality of sub frames having a display period of time shorter than one frame period of time through the column data line;
• a first holding unit that
• configures an static dynamic random access memory (SRAM) together with the first switching unit, and
• holds sub frame data obtained by the sampling performed by the first switching unit;
• a second switching unit that causes the sub frame data held in the first holding unit to be output;
• and
• a second holding unit that
• configures a dynamic random access memory (DRAM) together with the second switching unit, and
• applies output data, in which memory content is rewritten according to the sub frame data which is held in the first holding unit and is input through the second switching unit, to the pixel electrode,
• a pixel control unit that performs an operation of
• repeating writing the sub frame data in the first holding unit in units of rows in the plurality of pixels,
• turning on the second switching units of all the plurality of pixels by a trigger pulse after the sub frame data is written in all the plurality of pixels, and
• rewriting memory content of the second holding units of the plurality of pixels according to the sub frame data that is held in the first holding unit, in units of sub frames;
• and
• a timing control unit that is composed of an inverter chain circuit that performs control such that a delay of a certain period of time is sequentially given to a timing at which the pixel control unit turns on the second switching unit in units of rows of pixels,
• wherein
• the timing control unit is composed of two inverter chain circuits whose output shift directions are opposite to each other and selecting switches for selecting one of the outputs of the two inverter chain circuits which are arranged in units of rows of pixels, and the selecting switches are connected to the second switching unit to perform switching of the selecting switches at interval of the sub frames.