Method and system of classifying defects on a wafer

A method of classifying defects on a wafer, comprising:

• receiving a first plurality of images from a first plurality of chips and a second plurality of images from a second plurality of chips acquired by a charged particle beam, wherein said first plurality of chips and said second plurality of chips having similar feature
• examining said first plurality of images and said second plurality of images, wherein at least a defective image is found from one of said first plurality of images, and at least a defect-free image are is found from one of said second plurality of images, and said defective image shows at least one defect on a said one of said first plurality of chips;
• translating said defect-free image into a simulated layout that corresponds to a real layout of said one of said second plurality of chips, wherein said defect-free image has at least a pattern, said simulated layout represents an outer border of said pattern and is generated by connecting a first pixel and a second pixel and both said first pixel and said second pixel are located on said outer border of said pattern;
• and
• comparing said defective image with said simulated layout to classify said defect on said one of said first plurality of chips.

A system for classifying defects on a wafer, comprising:

• a receiving module for receiving a plurality of images acquired by a charged particle beam, wherein said images respectively correspond to a plurality of chips having similar feature on an examined wafer;
• an examining module electrically connected with said receiving module for examining said images to find at least a defect-free image and at least a defective image, wherein said defective image has at least one defect feature corresponding to a defect on one of said plurality of chips;
• a translating module electrically connected with said examining module for translating said defect-free image into a simulated layout that corresponds to a real layout of said plurality of chips, wherein said defect-free image has at least a pattern, said simulated layout represents an outer border of said pattern and is generated by connecting a first pixel and a second pixel and both said first pixel and said second pixel are located on said outer border of said pattern;
• and
• a comparing module electrically connected with said examining module and said translating module for comparing said defective image with said simulated layout to classify said defect on said one of said plurality of chips.