System coherency in a distributed graphics processor hierarchy

A graphics processor comprising:

• a physically distributed set of compute slices to execute a plurality of work items, wherein each compute slice includes a plurality of execution blocks each having a plurality of execution units;
• and
• a cache fabric to maintain a coherency of one or more memory lines associated with the plurality of work items across the graphics processor, a system memory and one or more host processors, wherein the cache fabric includes:
• a plurality of level one (L1) caches, each L1 cache being dedicated to an execution block of a compute slice, wherein each compute slice has a plurality of execution blocks;
• a physically distributed shared cache structure, wherein the coherency of the one or more memory lines is to be maintained across the plurality of L1 caches and the shared cache structure across the physically distributed set of compute slices, wherein the shared cache structure includes a level two (L2) cache having a plurality of banks, and wherein the shared cache structure is to hash at least one of the one or more memory lines across the plurality of banks;
• and
• a plurality of crossbar nodes to track the one or more memory lines, each crossbar node being dedicated to a compute slice and each crossbar node of the plurality of crossbar nodes being connected to the L1 cache of each of the plurality of execution blocks of the compute slice to which the crossbar node is dedicated.

A system comprising:

• a display to present visual content;
• and
• a graphics processor including:
• a physically distributed set of compute slices to execute a plurality of work items associated with the visual content, wherein each compute slice includes a plurality of execution blocks each having a plurality of execution units, and
• a cache fabric to maintain a coherency of one or more memory lines associated with the plurality of work items across the graphics processor, a system memory and one or more host processors, wherein the cache fabric includes:
• a plurality of level one (L1) caches, each L1 cache being dedicated to an execution block of a compute slice, wherein each compute slice has a plurality of execution blocks;
• a physically distributed shared cache structure, wherein the coherency of the one or more memory lines is to be maintained across the plurality of L1 caches and the shared cache structure across the physically distributed set of compute slices, wherein the shared cache structure includes a level two (L2) cache having a plurality of banks, and wherein the shared cache structure is to hash at least one of the one or more memory lines across the plurality of banks;
• and
• a plurality of crossbar nodes to track the one or more memory lines, each crossbar node being dedicated to a compute slice and each crossbar node of the plurality of crossbar nodes being connected to the L1 cache of each of the plurality of execution blocks of the compute slice to which the crossbar node is dedicated.

A method of operating a graphics processor, comprising:

• executing, by a physically distributed set of compute slices, a plurality of work items, wherein each compute slice includes a plurality of execution blocks each having a plurality of execution units;
• maintaining, by a cache fabric, a coherency of one or more memory lines associated with the plurality of work items across the graphics processor, a system memory and one or more host processors;
• hashing at least one of the one or more memory lines across a plurality of banks of a level two (L2) cache;
• and
• tracking, by a plurality of crossbar nodes, the one or more memory lines, wherein the coherency of the one or more memory lines is maintained across a plurality of level one (L1) caches and a physically distributed cache structure across the physically distributed set of compute slices, each L1 cache being dedicated to an execution block of a compute slice and each crossbar node being dedicated to a compute slice having a plurality of execution blocks and being connected to the L1 cache of each of the plurality of execution blocks.