Physically unclonable fuse using a NOR type memory array

A method providing an unclonable identifying chip comprising:

• forming a memory array, consisting of memory cells arranged in a matrix, each memory cell having two NMOS transistors, wherein a gate of the NMOS transistors in each row is coupled to a wordline, and a source of a first one of the two NMOS transistors in each column is coupled to a true bitline, and a source of a second one of the two NMOS transistors in each column is coupled to a complement bitline, and a drain of the two NMOS transistors is coupled to a source line having a voltage (VDD);
• activating the wordline, and forcing a voltage to the true and the complement bitlines to a predetermined voltage, the predetermined voltage being lower than the voltage VDD,
• wherein a threshold voltage of at least one of the NMOS transistors of the memory cell is increased by providing the at least one of the NMOS transistors with a charge trapping in response to applying an elevated wordline voltage to the activated wordline, and providing a voltage higher than the voltage VDD to the source line and forcing a corresponding bitline to ground (GND) during the activation of the wordline;
• floating the true and the complement bitlines;
• precharging the bitline through the NMOS transistor coupled to the activated wordline;
• and
• sensing a differential voltage of the true and the complement bitlines,
• wherein random binary strings are generated by sensing results of the differential bitline voltage.