Method and apparatus for determining common node logical connectivity
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorStephen Dixon
Life of this patent
Estimating the term…
Abstract
A method, system, and computer-readable medium are described that enable efficient design processes for integrated circuits. In particular, tools are described which enable an integrated circuit designer to visualize an integrated circuit design without combinational logic and, from such visualization, identify locations in the design of common node logical connectivity. This information enables the designer to identify potential areas where the integrated circuit design can be improved.
Claims23
A method for presenting synchronous cell connectivity in a semiconductor chip design, the method comprising:
- receiving, at a microprocessor, a semiconductor chip design that comprises a plurality of objects therein, the objects including at least one of blocks, modules, macros, and cells;
- bypassing, with the microprocessor, combinational logic of the objects in the semiconductor chip design to obtain a representation of the semiconductor chip design that includes connectivity of synchronous cells and ports thereof;
- and
- providing, with the microprocessor, a presentation of the semiconductor chip design based on the representation of the semiconductor chip design with the bypassed combinational logic of the objects.
A non-transitory computer-readable medium comprising processor-executable instructions that, when executed by a processor enable a presentation of synchronous cell connectivity in a semiconductor chip design, the instructions comprising:
- instructions configured to receive a semiconductor chip design that comprises a plurality of objects therein, the objects including at least one of blocks, modules, macros, and cells;
- instructions configured to bypass combinational logic of the objects in the semiconductor chip design to obtain a representation of the semiconductor chip design that includes connectivity of synchronous cells and ports thereof;
- and
- instructions configured to provide a presentation of the semiconductor chip design based on the representation of the semiconductor chip design with the bypassed combinational logic of the objects.
A system that enables presentation of synchronous cell connectivity in a semiconductor chip design, the system comprising:
- a microprocessor configured to execute computer-readable instructions;
- and
- computer memory having instructions stored thereon that enable the microprocessor to:
- receive a semiconductor chip design that comprises a plurality of objects therein, the objects including at least one of blocks, modules, macros, and cells;
- bypass combinational logic of the objects in the semiconductor chip design to obtain a representation of the semiconductor chip design that includes connectivity of synchronous cells and ports thereof;
- and
- provide a presentation of the semiconductor chip design based on the representation of the semiconductor chip design with the bypassed combinational logic of the objects.
Dependencies are inferred from the claim text.