Layout verification method and verification apparatus

A verification apparatus for verifying a characteristics change in a semiconductor integrated circuit, the verification apparatus comprising a computer configured to perform a process including:

• executing a timing analysis of the semiconductor integrated circuit based on first layout information acquired after execution of a layout process of the semiconductor integrated circuit;
• executing layout correction with respect to the first layout information;
• comparing the first layout information acquired before the execution of the layout correction and second layout information acquired after the execution of the layout correction to acquire information indicating an RC difference in wires of the semiconductor integrated circuit before and after the execution of the layout correction;
• and
• adding an effect due to an increase in delay in the wires resulting from the RC difference to timing information obtained by the timing analysis.

A non-transitory computer-readable medium storing a program for verifying a characteristics change in a semiconductor integrated circuit, the program, when executed by a processor, causes the processor to execute a process including:

• executing a timing analysis of the semiconductor integrated circuit based on first layout information acquired after execution of a layout process of the semiconductor integrated circuit;
• executing layout correction with respect to the first layout information;
• comparing the first layout information acquired before the execution of the layout correction and second layout information acquired after the execution of the layout correction to acquire information indicating an RC difference in wires of the semiconductor integrated circuit before and after the execution of the layout correction;
• and
• adding an effect due to an increase in delay in the wires resulting from the RC difference to timing information obtained by the timing analysis.