US 9,436,792 B2 · Method of designing layout of integrated circuit and method of manufacturing integrated circuit

Abstract

A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

Claims17

Dependent claims

A computer-implemented method of fabricating an integrated chip (IC), the method comprising:

designing a first layout by placing and routing a plurality of standard cells that define the IC;
generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns corresponding to a first layer of the first layout, such that a single mask is applied to the connected first and second patterns, thereby reducing the number of masks necessary for forming the first layer patterns of the first layer of the IC;
and
manufacturing the IC according to the second layout.

1 more element

A method of designing a layout of a standard cell of an integrated circuit (IC), the method comprising;

configuring a first layout by placing and routing a standard cell, the standard cell including first and second patterns from among first layer patterns corresponding to a first layer of the first layout;
configuring a second layout by modifying the first layout by connecting the first and second patterns among the first layer patterns so that the number of masks required to form the first layer patterns of the standard cell according to the second layout is reduced relative to the number of masks required to form the first layer patterns of the standard cell according to the first layout;
and
manufacturing the integrated circuit based on the second layout.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

14/820,983Filed 7 Aug 2015 · us provisional application

Priority

KR 10-2015-00305514 Mar 2015

Published

US 2016/0055286 A125 Feb 2016

Granted

6 Sep 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/394
Circuit design at the physical level: routing
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G03F 1/00
Originals for photomechanical production of textured or patterned surfaces

Method of designing layout of integrated circuit and method of manufacturing integrated circuit

Life of this patent

Method of designing layout of integrated circuit and method of manufacturing integrated circuit

Life of this patent

Abstract

Claims17