Structure, method and system for complementary strain fill for integrated circuit chips

A computer system comprising:

• a processor;
• and
• a computer-readable memory device coupled to communicate with said processor, said memory device containing instructions that, when executed by the processor, implement a method for complementary strain fill for integrated circuit chips by:
• generating an integrated circuit chip design for an integrated circuit chip;
• generating a tensile layer etch mask design for an etch mask used to etch a tensile stressed dielectric layer as specified in said integrated circuit chip design;
• generating a second mask design for an etch mask used to etch a compressive stressed dielectric layer as specified in said integrated circuit chip design;
• identifying active regions of an integrated circuit having a plurality of field effect transistors (FETs) distributed among a plurality of n-channel field effect transistors (nFETs) and a plurality of p-channel field effect transistors (pFETs);
• identifying low field effect transistor (FET) density regions of said integrated circuit design, said low FET density regions containing less than 10% FETs by area;
• placing fill shapes in said layer etch mask design and in said compressive layer etch mask design, said fill shapes placed only in respective regions of said tensile layer etch mask design and said compressive layer etch mask design corresponding to said low FET density regions, and said fill shapes defining areas of said tensile stressed dielectric layer to be removed from said integrated circuit chip fabricated based on said tensile layer etch mask design and areas of said compressive stressed dielectric layer to be removed from said integrated circuit chip fabricated based on said compressive layer etch mask design;
• and
• storing said tensile and compressive etch mask designs on a computer readable device.