US 9,436,788 B2Granted

Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformity

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsJyuh-Fuh Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Shy-Jay Lin, Burn Jeng Lin

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Abstract

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.

Claims19

Dependent claims

An integrated circuit (IC) method comprising:

receiving an IC design layout including a plurality of main features;
choosing isolation distances to the IC design layout;
oversizing the main features according to the isolation distances;
generating a space block layer for the isolation distances by a Boolean operation, according to the oversized main features;
choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout;
calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout, wherein the choosing of the optimized space block layer and the optimized block dummy density ratio includes choosing the optimized space block layer and the optimized block dummy density ratio according to the LVBDDR, wherein the calculating of the LVBDDR includes determining the LVBDDR r0 by a formula
r0=(PD0·PDs−PD0·PDs)/σs2,
where
PD0, is an average of the main pattern density;
PDs is an average of the dummy pattern density;
and
σs is a standard deviation defined by
σs2=PDs2−(PDs)2;
and
generating dummy features in the optimized space block layer according to the optimized block dummy density ratio.

12 more elements

An integrated circuit (IC) method comprising:

receiving an IC design layout designed to have a plurality of main features to be formed on a semiconductor substrate;
choosing isolation distances to the IC design layout;
oversizing the main features according to the isolations distances;
generating space block layers by a Boolean operation to the IC design layout, wherein each of the space block layers is associated with one of the isolation distances;
dividing the semiconductor substrate into a plurality of templates;
calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout to the plurality of templates for each of the space block layers;
calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for the each of the space block layers according to the main pattern density and the dummy pattern density;
choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR;
generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio;
and
forming a tape-out data of the modified IC design layout for IC fabrication,
wherein the calculating of the LVBDDR includes determining the LVBDDR r0 by a formula
r0=(PD0·PDs−PD0·PDs)/σs2,
where
PD0 is an average of the main pattern density;
PDs is an average of the dummy pattern density;
and
σs is defined by a formula
σs2=PDs2−(PDs)2.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/253,282Filed 15 Apr 2014
Published: US 2015/0294057 A115 Oct 2015
Granted: 6 Sep 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G06F 30/20
Computer-aided design [CAD]: design optimisation, verification or simulation
G06F 30/39
Circuit design: circuit design at the physical level
G03F 1/36
Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles…

Family

US 2015/0294057 A1Pre-grant publication · published 15 Oct 2015
US 9,436,788 B2This patent

From the US filing history. Foreign family members aren’t listed.

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