Architecture for vector memory array transposition using a block transposition accelerator

A system for vector memory array transposition, the system comprising:

• a vector memory to store a vector memory array;
• a block transposition accelerator coupled to the vector memory, the block transposition accelerator configured to firstly read vectors of a block of data by shifting the vectors into the vector memory array along a first dimension such that each vector is shifted serially into the vector memory in the same direction as the first dimension and to secondly write a transposition of the vectors by shifting the transposition of the vectors out of the vector memory along a second dimension such that each transposed vector is shifted serially out of the vector memory in the same direction as the second dimension, wherein the second dimension is perpendicular to the first dimension in the vector memory array;
• a vector input switch coupled to the block transposition accelerator;
• and
• an address controller coupled to the block transposition accelerator, the address controller configured to determine a vector access order,
• wherein the block transposition accelerator is configured to access the vector of the block of data within the vector memory array according to the vector access order;
• and
• wherein the vector input switch is configured to input the vector of the block of data from the vector memory to the block transposition accelerator in response to a read command from the block transposition accelerator.

A system for vector memory array transposition, the system comprising:

• a vector memory to store a vector memory array;
• a block transposition accelerator coupled to the vector memory, the block transposition accelerator configured to firstly read vectors of a block of data by shifting the vectors into the vector memory array along a first dimension such that each vector is shifted serially into the vector memory in the same direction as the first dimension and to secondly write a transposition of the vectors by shifting the transposition of the vectors out of the vector memory along a second dimension such that each transposed vector is shifted serially out of the vector memory in the same direction as the second dimension, wherein the second dimension is perpendicular to the first dimension in the vector memory array;
• and
• an address controller coupled to the block transposition accelerator, the address controller configured to determine a vector access order,
• wherein the block transposition accelerator is configured to access the vector of the block of data within the vector memory array according to the vector access order;
• and
• wherein the block transposition accelerator comprises a set of switched register chains, and
• wherein the vector is read into a column of the switched register chains, and the transposition of the vector is read out of the switched register chains.

A method for transposing a vector memory array, the method comprising:

• reading a plurality of vectors of a block of data within the vector memory array stored in a vector memory;
• appending a plurality of virtual segments to the vector memory array in response to a determination that the vector memory array has a width which is different from an instinctive vector width of a corresponding vector processing architecture
• reading, by a first block transposition accelerator in input mode, the plurality of vectors of the block of data into the first block transposition accelerator by separately shifting each one of the plurality of vectors of the block of data serially into separate rows of a plurality of matrix registers in a first direction;
• and
• outputting immediately after reading, by the first block transposition accelerator in output mode, a plurality of transposed vectors of the block of data serially from columns of the plurality of matrix registers that are perpendicular to the rows, wherein the plurality of transposed vectors are based on the plurality of vectors of block data.